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Curs VHDL 1   2

1. Protectia muncii. Prezentare laborator. Cerinte minimale.
2. Introducere mediu de programare FPGA Xilinx ISE
4. Unitate ALU pe 4 biti .... modificati pentru 2 biti
5. Decodificator 7 segmente        
7.  Numarator 8 biti  - modificati numaratorul din arhiva sa fie pe 8 biti si afisati continutul pe cele 8 leduri.

   8.1 Implementarea numaratoae/divizoare
   8.2 Implemntarea multiplexarii digitilor
   8.3 Implementarea tuturor functiilor pentru ceas

library IEEE;
entity div is
Port ( clock : in STD_LOGIC;
ledg: out std_logic;
reset:in std_logic;
clock_div_1hz: buffer STD_LOGIC;
clock_div_1khz: buffer STD_LOGIC);
end div;
architecture Behavioral of div is
signal div2: integer;
p2_1s:process(reset, clock, div2)
if reset ='1' then
div2<= 0;
elsif clock'event and clock='1' then
div2 <= div2+1;
end if;
if div2 = 25000000 then
clock_div_1hz <='1';
elsif div2 = 50000000 then
clock_div_1hz <='0';
end if;
if div2 = 50000000 then
div2<= 0;
end if;
end process;
end Behavioral;

 Microcontroler 8 biti PicoBlaze  HowTo1  HowTo2 HowTo3

In the laboratory practice, we use the free version of the Xilinx ISE 14.7 development environment called WebPack. The installer can be downloaded from the Xilinx website after registration (Xilinx ISE - Full Installer for Windows (TAR/GZIP - 6.18 GB)). The WebPack (free) licence could be obtained also from the Xilinx product licensing site. The software doesn't work on 64 bites Windows 8, 8.1 and 10. The problem can be solved as is presented here (There are also two youtube links that present the solution), or you can try the programm that can be downloaded from here.